1. Technical Field
The disclosure relates to an analysis method for a signal, and more particularly to an analysis method for a signal time margin.
2. Related Art
Generally, in a digital circuit, a clock signal has to latch data on a signal line in a specific time period, so as to perform corresponding processing. The specific time period is generally defined as a setup time margin and a hold time margin.
Along with the ever increasing clock speed of the digital signal, an Inter Symbol Interference (ISI) phenomenon caused by signal reflection and loss becomes more and more obvious. When different bit combinations are transmitted on the signal line, different waveform distortions are caused more seriously. Therefore, setup time margins and hold time margins calculated according to different bit cycles are different, that is, different data bits have their setup time margins and hold time margins, so that it is harder and harder to estimate the minimum setup time margin and the minimum hold time margin of the signal.
In order to obtain the minimum setup time margin and the minimum hold time margin so as to ensure the completeness and reliability of the product design, a large quantity of data bits are used in signal simulation software in a conventional manner. However, this conventional manner requires a lot of time to simulate various data bit combinations, and is also unable to find out the minimum setup time margin and the minimum hold time margin. Therefore, the analysis method for the setup time margin and the hold time margin is necessary to be improved.